1. Field of the Invention
The invention relates in general to a comparator. More particularly, this invention relates to a comparator having the self-calibration function of eliminating the input offset voltage.
2. Description of the Related Art
In various kinds of analog/digital converters (ADC) such as flash ADC, interpolation ADC, pipeline ADC and two-step ADC, a high speed comparator is often required to fulfill the requirements of high speed operation of the digital circuit.
FIG. 1 shows a circuit diagram of a conventional comparator. In FIG. 1, a PMOS latchp1114, a PMOS latchp2112, an NMOS latchn1120 and an NMOS latchn2118 are a set of regeneration stage circuits in the comparator 128. A PMOS resetp1116 and a PMOS resetp2110 are a set of reset circuits. An NMOS minm 122 and an NMOS minp 124 are a set of analog signal amplifiers, and an NMOS strb 126 is a switch determining whether the current of the whole comparator 128 is conducted.
In FIG. 1, when the low level latch signal is input from the latch terminal of the comparator 128, the NMOS strb 126 is open, and the NMOS resetp1116 and the PMOS resetp2110 are conducted. Thus, the output terminals outp and outm are reset to a voltage of vdda. When a high level latch signal is input from the latch terminal of the comparator 128, the NMOS strb 126 is conducted, and the NMOS resetp1116 and the PMOS resetp2110 are open. Therefore, the PMOS latchp1114, the PMOS latchp2112, the NMOS latchn1120 and the NMOS latchn2118 are regenerating. The input analog signal at the input terminal inp of the NMOS minp 124 is compared to the input analog signal at the input terminal inm of the NMOS minm 122 until the potential levels between the output terminals outp and outm are distinguished from each other.
If mismatch occurs to the NMOS minm 122 and the NMOS minp 124, or to the PMOS latchp1114, the PMOS latchp2112, the NMOS latchn1120 and the NMOS latchn2118 of the regeneration circuit, a large input offset voltage is caused at the input terminals inp and inm. The accuracy of the comparator 128 is thus seriously affected. In the actual circuit design, one can increase the transistor size to reduce the degree of mismatch, however the fabrication cost is raised, the power consumption is increased, and the operation speed is reduced (since the parasitic capacitance is increased).